1. Field of the Invention
This invention relates to semiconductor fabrication technology, and more particularly, to a method of fabricating a data-storage capacitor for a dynamic random-access memory (DRAM) device.
2. Description of Related Art
A computer system typically includes a central processing unit and a memory unit. Presently, the DRAM (dynamic random access memory) is widely used as the primary memory of computer systems. Basically, each single DRAM cell is composed of a transfer field effect transistor (TFET) and a data-storage capacitor.
FIG. 1 is a schematic diagram showing the equivalent circuit representation of a single DRAM cell. As shown, a single DRAM cell is composed of a TFET T and a data-storage capacitor C. The data-storage capacitor C is composed of two electrodes 100, 102 and a dielectric layer 101 sandwiched between the two electrodes 100, 102. By convention, the electrode 100 connected to the TFET is called a storage electrode, while the opposing electrode 102 is called a cell electrode. The TFET T is connected in such a manner that its gate is connected to a word line WL, its source (or drain) is connected to a bit line BL, and its drain (or source) is connected to the storage electrode 100. Whether the DRAM cell stores a binary value 0 or 1 is dependent on whether the data-storage capacitor C is charged or uncharged. If uncharged, it represents the storage of a first binary value, for example 0. Otherwise if charged, it represents the storage of a second binary value, for example 1. The data stored in the DRAM cell can be accessed via the word line WL and the bit line BL. The voltage state on the word line WL controls the ON/OFF state of the TFET T. When the TFET T is ON, data can be either read out from or stored into the data-storage capacitor C via the bit line BL.
In the fabrication of DRAMs having less than 1 MB (megabit) in storage capacity, it is a customary practice to utilize a two-dimensional capacitor called a planar-type capacitor as the data-storage capacitor for each DRAM cell. However, since the planar-type capacitor takes quite a large layout area on the substrate to implement, it is unsuitable for use in very large integration DRAMs. For 4 MB or higher DRAMs, a three-dimensional capacitor such as a stacked-type or a trench-type capacitor, is utilized instead.
Compared to the planar-type capacitor, both the stacked-type and the trench-type capacitors can provide a larger capacitance that allows the DRAM device to be further downsized while nonetheless allowing good charge (data)-retaining capability. However, when it comes to 64 MB or higher DRAMs, both the stacked-type and the trench-type capacitors also become inadequate.
One solution to the foregoing problem is to utilize the so-called fin-type capacitor, which has a very large capacitance due to the forming of a stacked structure of a plurality of horizontally-extended conductive layers that are formed into a fin-like shape to serve as the storage electrode. Research on the fin-type capacitor is published in the paper entitled "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" by Ema et al., International Electron Devices Meeting, pp. 592-595, December 1988. Moreover, patents that disclose methods for fabricating fin-type capacitors include U.S. Pat. Nos. 5,071,783; 5,126,810; and 5,206,787, to name a few.
Another solution for 64M DRAMs is to utilize the so-called cylindrical-type capacitor, which can provide a very large capacitance due to the forming of a vertically extended and cylindrically shaped electrode structure. This structure can help increase the surface area of the electrode, thereby increasing the capacitance of the capacitor. Research on the cylindrical-type capacitor is published in the paper entitled "Novel Stacked Capacitor Cell for 64-Mb DRAM", by Wakamiya et al., in the 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. Moreover, U.S. Pat. No. 5,077,688 discloses a method for fabricating a cylindrical-type capacitor.
With the trend toward high integration for DRAMs, the various circuit components in the DRAMs, including the data-storage capacitors, must be reduced in size. However, the downsizing of a capacitor also means that the capacitance of the downsized capacitor is reduced, which causes the charge retaining capability of the downsized capacitor to be reduced. The data retaining capability of the downsized DRAM may thus be unreliable. Moreover, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of .alpha.-rays increases. Therefore, there still exits a need in the DRAM industry for a new method that can be used to fabricate a data-storage capacitor in a downsized DRAM device while nonetheless provide an adequate capacitance.